1. Field of the Invention
The present invention relates to a signal processing circuit for adjusting signal amplitude, and more particularly, to a signal processing circuit that selectively enables an attenuator or a gain controllable amplifier coupled in parallel so as to reduce power consumption when converting signal formats of related input signals.
2. Description of the Related Art
The most important characteristics of the modern information society is that every kind of information and knowledge is transmitted, stored, or manipulated in the form of electrical signals. Information in an electrical signal form can be accumulated and be exchanged rapidly, and technology keeps progressing based on the ability to manipulate information in electrical circuits. Basically, information in electrical form cannot be properly manipulated until an electrical circuit adjusts this information into digital form. For example, a reflected signal from a loaded optical disc, which is then read by an optical pickup head, cannot be suitably processed if its format is not converted into a digital format. Since different optical disc drivers usually have different gains at their integrated laser generator and the optical pickup head, and each optical disc usually has a different reflection rate, these different gains and reflection rates will affect the signal amplitude of the reflected one to deviate from the normal. For the sake of adjusting different signal amplitudes and for guaranteeing the adjusted amplitude to be converged within a predetermined value so as to ensure that the input signal can be transformed as a digital form correctly, a conventional signal processing circuit 10 is provided to adjust the signal amplitude and generate a corresponding output signal for further data processing and applications. The conventional signal processing circuit 10 implemented in optical disc drivers is used to process the input signal transformed from the reflected signal aforementioned.
Please refer to FIG. 1, which is a circuit block diagram illustrating a conventional signal processing circuit 10 including an attenuator 16, a gain controllable amplifier 18, a control unit 14, a peak detector circuit 22 and a waveform adjuster circuit 24. The input signal 12 enters to the conventional signal processing circuit 10 shown in FIG. 1 in a differential signal form such that the conventional signal processing circuit 10 also deals with this signal in a differential way. The attenuator 16 receives the input signal 12 through input ends 14A and 14B and then outputs related attenuated signal to the gain controllable amplifier 18. The gain controllable amplifier 18 receives the attenuated signal delivered from the attenuator 16 through input ends 16A and 16B and then outputs an amplified output signal 26 to both the waveform adjuster circuit 24 and the peak detector circuit 22. The gain controllable amplifier 18 has a control pin 20 that receives a control signal provided by the control unit 14. The peak detector circuit 22 is basically a signal envelope detector for evaluating the envelope amplitude of the input signal at the input ends 22A and 22B, then outputting the evaluated envelope amplitude through an output end. Input ends 22A and 22B of the peak detector circuit 22 receive the amplified output signal 26 from the gain controllable amplifier 18, and the output end of the peak detector circuit 22 is connected to the control unit 14. The control unit 14 has an input end and an output end, wherein the output end is connected to the control pin 20 of the gain controllable amplifier 18. The control unit 14 can be a digital signal processor (DSP) or a microprocessor containing internal default values (or thresholds). Please note that the envelope amplitude is the difference between the signals at the input ends 22A and 22B, while the default values or thresholds are used for comparing with the evaluated envelope amplitude so as to determine whether the signals passing through the input ends 22A and 22B are too large or too small. Accordingly, the control unit 14 adjusts the gain of the gain controllable amplifier 18 through the control pin 20 according to the comparison result. The waveform adjuster circuit 24, functioning like a data slicer, can properly transfer an analog signal into a digital one based on a predetermined slice level. The waveform adjuster circuit 24 encompasses input ends 24A and 24B for receiving the output signal 26, and an output end for outputting a digital signal.
The conventional signal processing circuit 10 works as follows. The input signal 12 enters the conventional signal processing circuit 10 via input ends 14A and 14B of the attenuator 16. Firstly, the attenuator 16 attenuates this input signal 12 to restrict the input signal 12 to the input range of the gain controllable amplifier 18. Next, the attenuated signal is transmitted to the gain controllable amplifier 18 in differential form, while the gain controllable amplifier 18 amplifies the attenuated signal and then delivers this amplified one as an output signal 26. This output signal 26 is also transmitted to the peak detector circuit 22 while it is transmitted simultaneously to the waveform adjuster circuit 24 for further processing. The peak detector circuit 22 evaluates the envelope amplitude of the output signal 26 and transmits the evaluated envelope amplitude of the to the control unit 14. The control unit 14 adjusts the gain of the gain controllable amplifier 18 via the control pin 20 according to the evaluated envelope amplitude of the output signal 26. The conventional signal processing circuit 10 can modulate the gain of the gain controllable amplifier 18 and can thus adjust the amplitude of the output signal 26 by means of the control unit 14. If the evaluated envelope amplitude of the output signal 26 is too small, the control unit 14 will increase the gain of the gain controllable amplifier 18 so as to increase that of the output signal 26. Similarly, the control unit 14 will decrease the gain of the gain controllable amplifier 18 if the evaluated envelope amplitude of the output signal 26 is too large.
However, the conventional signal processing circuit 10 has the following drawbacks. The first one is that the attenuator 16 and the gain controllable amplifier 18 work simultaneously, that is, they both consume power while the input signal 12 is being format-converted. The second one is that the input signal 12 is firstly processed by the attenuator 16 and then by the gain controllable amplifier 18, so the gain of the gain controllable amplifier 18 must be large enough to compensate a loss caused by the attenuator 16. Those skilled in the art know that the gain controllable amplifier 18 has a fixed gain-bandwidth product. That is to say, it is impossible to increase the gain of the gain controllable amplifier 18 without decreasing the bandwidth of the gain controllable amplifier 18. Therefore, the effective working bandwidth of the conventional signal processing circuit 10 is restricted by the bandwidth of the gain controllable amplifier 18. The conventional signal processing circuit 10 does not normally operate on high frequency signals or on high information density signals.